High-speed implementation of ANT series block cipher algorithm on FPGA

Abstract

ANT series block cipher algorithm is suitable for lightweight implementation and convenient for side channel protection. For ANT-128/128 algorithm, Verilog HDL is used to implement the key expansion module and encryption module in Quartus II 15.0, and a 46-level pipeline structure is adopted for high-speed optimization. Further, the pipeline structure was used for high-speed optimization. The comprehensive results in chip 5CGXFC7D6F31C7ES of Cyclone V show that the implementation results are consistent with the standard vector value. The logic utilization ratio of the two modules only accounts for 3% and 7% of the total resources respectively. The working frequency of the encryption and decryption module based on pipeline structure can reach up to 339 MHz and the data throughput rate can reach up to 43 Gbps.

Keywords

• ant
• block cipher
• verilog hdl
• pipeline structure