Chip Power-Frequency Scaling in 10/7nm Node

Abstract

The 10/7nm node has been introduced by all major semiconductor manufacturers (Intel, TSMC, and Samsung Electronics). This article looks at the power-performance benefit of the 10/7nm node as compared to the previous node (14nm). Specifically, we track the power-performance in high performance space, using Intel's Core-i7 (Intel's highest performance consumer microprocessor that uses the highest performance CMOS technology node) manufactured in Intel's 10nm. The paper first looks at the scaling of the device power-performance from the Intel 14++nm node to Intel 10nm, using 3D TCAD simulation with dimensions obtained from actual product cross-sections, and also scaling of the interconnect capacitance node-to-node. Next, the paper does a comparison of industry 10/7nm node technologies (from Intel, TSMC, and Samsung Electronics). The paper argues that for Intel, in the 10nm nodes, the total chip power at constant frequency (energy-per-operation) has scaled by a much lower amount vs. the 14++ node, as compared to the 14++ vs. the previous (22 nm) node. The lack of power scaling can be traced to a reduction in current per device perimeter (caused by the increased device parasitic resistance and the reduced device and fin pitch) and to an increase in capacitance per fin (caused by an increase in the FinFET height). Proper scaling of the device is critical for chip power scaling (energy-per-operation) at upcoming nodes, especially as it applies to high performance microprocessors and for the data analyzed here this is not the case.

Keywords

• Computer performance
• CMOS scaling
• FinFET
• Moore’s Law
• MOSFET
• power dissipation