Hardware implementation of a novel edge-map generation technique for pupil detection in NIR images

Abstract

This paper proposes an edge-map generation technique for pupil detection in near infrared (NIR) images and its hardware implementation. The proposed edge-map generation technique is based on generating two different edge-maps of same eye image using Gaussian filtering, image binarization and Sobel edge detection operations and then combining them to a single edge-map using intersection operation on binary images. This technique reduces the false edges drastically in the edge-map of eye image, which is desirable for accurate and fast pupil detection. Field programmable logic array (FPGA) based hardware implementation of the proposed technique is presented, which can be used in iris localization system on FPGA based platforms for iris recognition application. The proposed edge-map generation hardware is a parallel-pipelined implementation.

Keywords

• Iris localization
• Pupil detection
• Edge-map generation
• FPGA based implementation
• Hardware implementation