Modeling of Surface Potential and Threshold Voltage of LDD nMOSFET's with Localized Defects

Abstract

We propose a model of the surface potential and the threshold voltage for submicron lightly-doped drain LDD nMOSFET’s in relation with the localized defects at the interface Si–SiO2 in the overlap n‾ LDD region. Calculating the surface potential in the intrinsic and the LDD regions by solving the 2-D Poisson's equation, the minimum surface potential and the threshold voltage model are derived. Simulation results show that the extension of the degraded zone induce a decrease of the surface potential and a modification on its profile, this leads to an increase of the threshold voltage. The threshold voltage variation can be used to characterize the ageing effect. The DIBL (Drain induced barrier lowering) and the substrate bias effects are also included in this model.