A Novel High-Speed Split-Gate Trench Carrier-Stored Trench-Gate Bipolar Transistor with Enhanced Short-Circuit Roughness

Abstract

A novel high-speed and process-compatible carrier-stored trench-gate bipolar transistor (CSTBT) combined with split-gate technology is proposed in this paper. The device features a split polysilicon electrode in the trench, where the left portion is equipotential with the cathode. This design mitigates the impact of the anode on the trench gate, resulting in a reduction in the gate-collector capacitance (CGC) to improve the dynamic characteristics. On the left side of the device cell, the P-layer, the carrier-stored (CS) layer and the P-body are formed from the bottom up by ion implantation and annealing. The P-layer beneath the trench bottom can decrease the electric field at the bottom of the trench, thereby improving breakdown voltage (BV) performance. Simultaneously, the highly doped CS layer strengthens the hole-accumulation effect at the cathode. Moreover, the PNP doping layers on the left form a self-biased pMOS. In a short-circuit state, the self-biased pMOS turns on at a certain collector voltage, causing the potential of the CS-layer to be clamped by the hole channel. Consequently, the short-circuit current no longer increases with the collector voltage. The simulation results reveal significant improvements in comparison with the conventional CSTBT under the same on-state voltage (1.48 V for 100 A/cm2). Specifically, the turn-off time (toff) and turn-off loss (Eoff) are reduced by 38.4% and 41.8%, respectively. The short-circuit current is decreased by 50%, while the short-circuit time of the device is increased by 2.46 times.

Keywords

• CSTBT
• split-gate technology
• high speed
• short-circuit roughness