Generation scheme of chirp scaling phase functions based on floating-point CORDIC processor

Abstract

This study presents a chirp scaling (CS) phase function generation scheme based on CORDIC algorithm, it adopts single precision floating-point CORDIC processor to implement a variety of non-linear operations which are involved in CS synthetic aperture radar (SAR) imaging algorithm. We extend the range of convergence of CORDIC algorithm and reduce the data width in rotation unit module by adopting a hardware resource reduction scheme. We also adopt a unified CORDIC processor to achieve square root, multiplication, and division operation, which can substitute multiple single-function processors and simplify the complicate arithmetic in CS algorithm. As a proof of concept, we verify the performance of the proposed design scheme on Xilinx XC7VX690T FPGA platform, it is also applied to 16384 × 16384 points target SAR imaging system, the FPGA resource occupancy of the CS phase function generation module demonstrates that the usage of CORDIC processor can effectively save the consumption of hardware resources, and the maximum operating frequency is acceptable. The accuracy of phase functions can satisfy the engineering requirements.

Keywords

• synthetic aperture radar
• floating point arithmetic
• field programmable gate arrays
• radar imaging
• logic design
• function generators
• chirp scaling phase functions
• chirp scaling phase function generation scheme
• cordic algorithm
• single precision floating-point cordic processor
• nonlinear operations
• hardware resource reduction scheme
• unified cordic processor
• division operation
• xilinx xc7vx690t fpga platform
• sar imaging system
• cs synthetic aperture radar imaging algorithm
• multiplication operation
• square root operation