High-Speed Fractal Image Compression Featuring Deep Data Pipelining Strategy

Abstract

A new architecture based on deep data pipelining is proposed for implementing fractal compression of high-resolution images in real time. The general idea is to partition an image into overlapping range and domain blocks in which four range blocks constitute one domain block. In this way, two matching operations can be performed simultaneously using two processor units. Further reduction in the encoding time is achieved by exploiting the inherently high degree of correlation among pixels in the neighborhood areas and restricting the search in the neighboring blocks only. The design is synthesized on Altera Stratix IV field-programmable gate array and optimized at circuit level in order to achieve a high-speed implementation. The proposed architecture is evaluated in terms of the peak signal-to-noise ratio (PSNR), the runtime, the memory utilization, and the compression ratio (CR). Experimental results suggest that the proposed architecture is able to encode a 1024 × 1024 size image in 10.8 ms with PSNR and CR averaging at 27 dB and 34:1, respectively. Meanwhile, the energy dissipation is approximately 0.5 W which is comparable to the state-of-the-art fractal processors.

Keywords

• Digital circuits
• field programmable gate arrays
• fractal image compression
• parallel architectures
• pipeline processing