SYNTHESIS AND REDUCED LOGIC GATE REALIZATION OF MULTI-VALUED LOGIC FUNCTIONS USING NEURAL NETWORK DEPLOYMENT ALGORITHM

Abstract

In this paper an evolutionary technique for synthesizing Multi-Valued Logic (MVL) functions using Neural Network Deployment Algorithm (NNDA) is presented. The algorithm is combined with back-propagation learning capability and neural MVL operators. This research article is done to observe the anomalistic characteristics of MVL neural operators and their role in synthesis. The advantages of NNDA-MVL algorithm is demonstrated with realization of synthesized many valued functions with lesser MVL operators. The characteristic feature set consists of MVL gate count, network link count, network propagation delay and accuracy achieved in training. In brief, this paper depicts an effort of reduced network size for synthesized MVL functions. Trained MVL operators improve the basic architecture by reducing MIN gate and interlink connection by 52.94% and 23.38% respectively.

Keywords

• Multi-valued logic
• Machine learning
• Back-propagation
• Training
• Synthesis
• Realization
• Neural network