An approach to Direct Memory Access module verification

Abstract

A method of direct memory access subsystem verification used for “Elbrus” series microprocessors has been described. A peripheral controller imitator has been developed in order to reduce verification overhead. The model of imitator has been included into the functional machine simulator. A pseudorandom test generator for verification of the direct memory access subsystem has been based on the simulator.

Keywords

• system verification
• functional model
• direct memory access
• pseudorandom test generation