Symbolic Analysis of Faulty Logic Circuits under Correlated Data-Dependent Gate Failures

Abstract

In this paper we present a method for symbolic analysis of unreliable logic circuits in the presence of correlated and data-dependent gate failures, described by Markov chains. Furthermore, using this method we investigate the influence of data-dependent failures on the performance of majority logic and multiple input XOR gates.

Keywords

• Combinatorial circuits
• fault-tolerance
• Markov chains
• symbolic analysis