Physically non-cloneable arbiter-type function with non-linear path pairs

Abstract

Physically unclonable functions (PUFs) are basic physical cryptographical primitives, providing to solve tasks such as unclonable identification, digital device authentication and copyright authentication, true random sequence generation, etc. The major features of PUFs are stability, unpredictability and irreproducibility, due to uncontrollable random variations of distinctive features of the raw materials and technological processes used during their manufacturing. Generally, PUF are digital circuits that extract such variations and convert them into a binary format, which applied for further use. Among the variety of PUF types, an Arbiter PUF (APUF) is distinguished, which is a digital circuit with N-bit challenge input and single output for one-bit response generation. The functionality of APUF is based on comparison of transition time of two copies of the test signal along a pair of configurable paths, selected by the challenge value CH from a set of 2N all possible pairs. The result of the comparison is the binary value of the response. The set of all challenge-response pairs is a random, unpredictable and irreproducible in the cases of implementation of cloned PUF circuits both on single and/or on another chips, also using different technologies. This article presents a new approach to the synthesis of the APUF circuits, based on the permutation network elements, which allow to construct the nonlinear structures of pair of paths. This implies the potential complication of building an APUF model to attack its implemented instances. This article presents new schematic solutions for the synthesis of APUF circuits. Also, the main characteristics of the proposed APUF circuits implemented on the Xilinx Zynq-7000 FPGA is analyzed.

Keywords

• physically unclonable functions
• arbiter
• permutation networks