Reconfigurable Hyper-Parallel Fast Fourier Transform Processor Based on Bit-Serial Computing

Abstract

The upcoming 5G communication is committed to providing ultra-high throughput and ultra-low delay service. However, digital signal processing technologies will be a critical challenge with the increasing bandwidth and transmitting streams. Especially, traditional fast Fourier transform (FFT) architectures are hard to meet the high-speed, high-performance, and low-overhead requirements. To overcome this issue, this article proposes a reconfigurable hyper-parallel bit-serial (HPBS) FFT processor. A bit-serial paradigm implements the datapath to reduce the hardware cost due to high parallelism as high as 64 to support FFT size from 64 to 2048. The HPBS design brings several significant advantages. Firstly, the hyper-parallel architecture supports large FTT radix with lower computation complexity, e.g., fewer processing stages and constant multipliers than conventional multipliers. Secondly, the bit-serial design enables the hyper-parallel FFT implemented by an acceptable hardware cost. Thirdly, the HPBS design supports the flexible and dynamic adjusting between latency and precision, which provides an additional optimization dimension. Based on the 55-nm process, the proposed 2048-point FFT can provide 32.128 Gbps throughput at 502MHz frequency with an average 12-bit word length. Besides, the normalized hardware efficiency can be up to 46.630 Gbps/mm2, which is at least 2X that of the traditional design.

Keywords

• Fast Fourier transform (FFT)
• bit-serial
• MIMO-OFDM
• mixed-radix factorization
• digital signal processing (DSP)