Reinforcement design of radar pulse compression algorithm in space-borne environment

Abstract

Realising radar high-speed real-time signal processing under the space-borne environment is a worldwide research difficult point. Commercial Quartus devices required for high-speed processing are hardened and consolidated in high radiation environments. This study realises high-speed real-time radar signal processing in space-borne environment for doing the reinforced design of commercial Quartus chip for pulse compression algorithm. The article first analysed the failure modes of high-performance FPGAs in a space-borne environment in China: a highly efficient parallel pipeline architecture with 8-8 K points is designed; control registers, state machine registers, on-chip RAM, and other easy-to-flip positions have been fully reinforced for the pulse compression algorithm. The system realises 200 M real-time processing capability after integration. Single-event fault injection tests were performed on key signals such as system control, and the test results verified the effectiveness of the reinforcement. The fault tolerance of the system has been significantly improved to ensure the normal operation of the FPGA.

Keywords

• fault tolerance
• field programmable gate arrays
• pulse compression
• signal processing
• radar signal processing
• highly efficient parallel pipeline architecture
• real-time processing capability
• reinforcement design
• radar pulse compression algorithm
• space-borne environment
• radar high-speed real-time signal processing
• high-speed processing
• high radiation environments
• high-speed real-time radar signal processing
• reinforced design
• high-performance FPGAs
• temperature 8.0 K to 8.0 K