On the comparison of memristor-transistor hybrid and transistor-only heterogeneous FPGAs

Abstract

Recently, memristor-CMOS based hybrid, homogeneous reconfigurable architectures have gained popularity as they offer better area results compared to their CMOS-only counterparts. But no work has been done on hybrid heterogeneous reconfigurable architectures (i.e. heterogeneous FPGAs). In this work, we design and simulate basic as well as complex memristor-transistor hybrid building blocks of heterogeneous island-style FPGA which are later combined together to construct complete hybrid heterogeneous FPGA architecture. Area comparison between hybrid and conventional building blocks of heterogeneous FPGA shows that hybrid blocks are 25–60% smaller compared to transistor-only blocks. For complete architecture level comparison, we propose an exploration flow which is built by combining several open source and indigenous tools. For experimentation and comparison between two FPGA architectures, two sets of open source heterogeneous benchmarks are used. These benchmarks are passed through our proposed flow to generate the area results for hybrid as well as conventional heterogeneous FPGA architectures. Area comparison results show that, on average, hybrid architecture requires 59% less area for two benchmark sets. Keywords: Heterogeneous FPGA, Memristor-transistor hybrid approach, Reconfigurable architectures, Exploration flow