IEEE Access (Jan 2025)

A Scalable 16-Element and 45.5 dBm-EIRP D-Band CMOS Phased-Array Transceiver Integrated With Antenna-in-Package for 6G Communications

  • Hyohyun Nam,
  • Hyeongjin Kim,
  • Sungjae Oh,
  • Jungsik Kim,
  • Chae Jun Lee,
  • Meeran Kim,
  • Hee Sung Lee,
  • Seung Hun Kim,
  • Jaekwang Kwon,
  • Kyeongho Yeom,
  • Dongjin Jung,
  • Dongki Kim,
  • Seong-Kyun Kim,
  • Dae Young Lee

DOI
https://doi.org/10.1109/ACCESS.2025.3539380
Journal volume & issue
Vol. 13
pp. 27007 – 27023

Abstract

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This paper presents a D-band 16-element phased-array transceiver IC with integrated dual-polarized antenna for 6G wireless communications. Fabricated in 28-nm CMOS, the transceiver operates with five component carriers (5CCs) supporting carrier aggregation in the 138–150 GHz range with 12 GHz bandwidth. The transceiver implements various circuit techniques to overcome the $f_{T}$ limitations of 28-nm CMOS, including differential amplifiers with cross-coupled capacitors and transformer-based inter-stage matching networks. The TX achieves a maximum EIRP of 45.5 dBm with saturated output power and demonstrates EVMs of 5.34-7.2% for 64-QAM signals at 30 Gbps. The RX exhibits less than 8 dB noise figure and achieves EVMs of 5.47-7.21% for 64-QAM signals at 24 Gbps. In over-the-air link testing at 2 m distance, the system achieves less than 4% EVM with both 64- and 256-QAM OFDM signals, representing the best performance reported to date for D-band CMOS implementations. The transceiver IC occupies 29.7 mm2 die area and consumes 3,681 mW and 747 mW for TX and RX operation, respectively.

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