An Extended Finite State Machine-Based Approach to Code Coverage-Directed Test Generation for Hardware Designs

Abstract

Model-based test generation is widely spread in functional verification of hardware designs. The extended finite state machine (EFSM) is known to be a powerful formalism for modelling digital hardware. As opposed to conventional finite state machines, EFSM models separate datapath and control, which makes it possible to represent systems in a more compact way and, in a sense, reduces the risk of state explosion during verification. In this paper, a new EFSM-based test generation approach is proposed and compared with the existing solutions. It combines random walk on a state graph and directed search of feasible paths. The first phase allows covering “easy-to-fire” transitions. The second one is aimed at “hard-to-fire” cases; the algorithm tries to build a path that enables a given transition; it is carried out by analyzing control and data dependencies and applying symbolic execution techniques. Experiments show that the suggested approach provides better transition coverage with shorter test sequences comparing to the known methods and achieves a high level of code coverage.

Keywords

• проектирование аппаратуры
• язык описания аппаратуры
• имитационная верификация
• генерация тестов
• моделирование
• расширенный конечный автомат
• обход графа
• случайный обход
• поиск с возвратами
• символическое исполнение
• разрешение ограничений