Design of high-speed image data transmission system based on DDR2

Abstract

In the high-speed image data transmission system, a high-speed image data transmission system design scheme based on DDR2 SDRAM is proposed for the high throughput of image data and the application of "large capacity" data buffer. In order to meet the high throughput requirements of image data and the large capacity requirements of data caching, FPGA internal FIFO resources with off-chip DDR2 hierarchical cache mechanism is adopted. In order to facilitate the reading and writing of image data and the management of addresses, the internal storage space of DDR is redistributed. After testing, the system can display image data in real time on the host computer, which is stable and reliable.

Keywords

• ddr2
• fpga
• hierarchical caching
• data transmission