High bandwidth data and image transmission using a scalable link model with integrated real-time data compression

Abstract

Our society increasingly relies on the transmission and reception of vast amounts of data using serial connections featuring ever-increasing bit rates. In imaging systems, for example, the frame rate achievable is often limited by the serial link between a camera and host even when modern serial buses with the highest bit rates are used. This paper reports a scalable link system with a bandwidth and interface standard that can easily be adapted to suit a particular application. The scalable serial link approach has been extended with lossless data compression with the aim of further increasing dataflow at a given bit rate. The compression method is integrated into the scalable transceivers providing a comprehensive solution for optimal data transmission over a variety of different interfaces. The system is fully implemented on an FPGA using a fully hardware based system. A Terasic DE4 board was used for implementing and testing the system using Quartus-II software and tools for design and debugging. The impact of compressing the image and carrying the compressed data through parallel lines is similar to the impact of compressed the same image inside a single core with a higher compression ratio, in this system between 7.5 and 126.8.

Keywords

• Real-time
• Transceiver system
• FPGA
• Embedded system