Efficient Implementation of Ternary SDM Filters using State-of-the-Art FPGA

Abstract

We present the analysis of a ternary FIR filter at varying OSR (Over Sampling Ratios). The sigma delta modulated ternary filter impulse responses obtained using Matlab at varying OSRs show that each doubling of OSR results in an increase of 10dB in the stopband attenuation. BT-FIR (Balanced Ternary FIR Filters) at varying OSRs have been implemented in VHDL using an efficient adder tree organization to gather the partial products. Filters in both pipelined and non-pipelined modes were synthesized on a small number of representative commercial FPGA (Field Programmable Gate Arrays) devices. Both the filter taps and binary inputs use 2\'s complement format. The synthesis results show the tradeoffs between hardware area and performance at varying OSRs. In pipelined mode, a 6MHz video stream can easily be handled at an OSR of 64, while occupying less than 8% of a Stratix-III device.

Keywords

• Ternary FIR filter
• FPGA
• Sigma Delta Modulation
• VHDL Implementation.