Decomposition Approaches for Power Reduction

Abstract

The article discusses a synthesis strategy aimed at reducing power consumption consumed by logic structures implemented in FPGAs. The essence of the method is to carry out multioutput function decomposition, which takes into account the problem of dynamic power reduction. The article presents several techniques leading to such a reduction: preliminary ordering of variables taking into account the probabilities of occurrence of the value 1 for individual variables, reduction of the number of LUTs by limiting the number of bound functions, and in particular bicoding or appropriate unicoding taking into account the need to reduce power for the implementation of multioutput functions. These techniques have been combined into a coherent synthesis strategy called PowerdekBDD, which is an extension of the DekBDD strategy, which is the result of many years of work in the area of logic synthesis using BDD graphs. The article contains the results of experiments confirming the effectiveness of the presented strategy.

Keywords

• Decomposition
• FPGA
• low power synthesis
• switching activity
• technology mapping