TRIO-TCAM: An Area and Energy-Efficient Triple-State-in-Cell Ternary Content-Addressable Memory Architecture

Abstract

Ternary content-addressable memory (TCAM) is critical for applications requiring high-speed data retrieval and pattern matching, such as networking, cybersecurity, artificial intelligence, and real-time data analytics. While recent advancements in TCAM architectures have addressed challenges related to power consumption and scalability, significant potential for further optimization remains, particularly in enhancing energy efficiency and cell density. In this paper, we introduce TRIO-TCAM, a novel area- and energy-efficient TCAM architecture that utilizes a 10-transistor SRAM cell. Building on and surpassing the performance of state-of-the-art (SOTA) designs, TRIO-TCAM, designed using 28nm FD-SOI technology, achieves a 7.6% reduction in cell area. Moreover, it reduces searching delay by up to 37.4%, searching energy per bit by as much as 67.6%, and cell leakage by more than 41.7% compared to SOTA designs. These advancements position TRIO-TCAM as a promising solution for high-density, low-power TCAM applications in future high-performance systems.

Keywords

• Ternary content addressable memory
• triple-state-in-cell
• TRIO-TCAM
• TRIO-SRAM
• 6T SRAM