Improving Energy Efficiency of Low-Voltage Logic by Technology-Driven Design

Abstract

Reducing VDD while keeping leakage current low is critical for minimizing energy consumption for systems across the compute-continuum, especially in IoT. Emerging low-VDD logic devices such as tunnel FET (TFETs) offer better low-VDD performance than conventional MOSFETs but lack performance at high-VDD. To assess TFETs, and other transistors optimized for low-VDD operation, we propose a technology-driven design framework. Our framework adapts standard industry flows and tools to optimize the design of logic blocks with full consideration of the tradeoffs possible with the future generation device I-V characteristics and interconnect. Proposed approach optimizes design implementation to improve projected power-performance and area, as well as, expected accuracy of the projections. TFET improves energy efficiency by 2.35× and 1.35× over MOSFET at low- and high-performance points, respectively, for industrial design test cases. Accuracy of the energy efficiency and performance projections is improved by 71% and 40%, respectively.

Keywords

• Cell library
• circuit-device interaction
• interconnect
• Internet of Things (IoT)
• synthesis
• tunnel FETs (TFETs)