Design of 12-bit 6 GS/s high speed DAC with>63 dB SFDR in InP HBT

Abstract

The paper presents a 12 bit 6 GS/s current-steering digital-to-analog converter(DAC) based on a 0.7 μm ft=280 GHz InP heterojunction bipolar transistor(HBT) technology. Current switch uses the new architecture to enlarge output impedance and make it stability. Besides, Deglitch circuit is used in DAC output to eliminate glitches generated during DAC switch flip, which can optimize the spurious-free-dynamic-range(SFDR). Simulation results show that the chip achieves a DNL/INL of 0.75/0.5 LSB respectively. The Deglitch circuit can increase the SFDR of the DAC by 10 dB at high frequencies, and achieve SFDR>63 dB over the whole Nyquist region, greatly improving the dynamic performance of the DAC.

Keywords

• digital-to-analog converter(dac)
• current-steering
• inp hbt
• deglitch
• spurious-free-dynamic-range(sfdr)