A 14.5-Bit ENOB, 10MS/s SAR-ADC With 2^nd Order Hybrid Passive-Active Resonator Noise Shaping

Abstract

A new 2nd order noise shaping (NS) based successive approximation register (SAR) ADC is presented in this paper. In comparison to earlier research, this paper considers hybrid passive-active integrators to compensate for the phase error of the passive integrator. To realize the resonator noise shaping in a high-speed asynchronous SAR-ADC, the hybrid passive-active sigma-delta modulator (SDM) is introduced as a multi-input, feed-forward loop filter. This overcomes the conventional asynchronous SAR-ADC noise barrier generated from the CDAC, quantizer, and dynamic comparator. The proposed noise shaping technique significantly reduces the ADC power consumption and area compared with the active SDM noise shaping approach. This circumvents the shortcomings of passive SDM, such as a large area, low resolution, and low speed. It consists of very low power, forward gain $G$ and positive feedback path across a 1st order passive switch capacitor (SC) integrator that desensitizes capacitor ratios under PVT variations. Extensive circuit simulation verifications and system-level results have been used to validate the effectiveness of the proposed NS SAR-ADC. The simulation results show that the proposed SAR ADC consumes 0.88mW at 10MS/s, with an SNDR of 89.43 dB and SFDR 98.64 dB within 0.1 fs oversampling frequency.

Keywords

• Discrete-time (DT)
• low-gain-amplifier-based switched-capacitor (SC) integrator
• noise shaping
• passive SC integrator
• sigma-delta modulator