In‐Depth Analysis of One Selector–One Resistor Crossbar Array for Its Writing and Reading Operations for Hardware Neural Network with Finite Wire Resistance

Abstract

This work provides a comprehensive analytical analysis of one‐selector‐one‐resistor (1S1R) crossbar array (CBA) device for hardware neural network (HNN) applications. Simplified analytical device models are prepared from a particular 1S1R device to validate the analysis. The read margin (RM) analysis results show that the V/3 voltage scheme and reduced selector leakage are necessary to maximize the RM and maximum operable size N of the CBA, where N indicates the number of wires (word line or bit line). The write margin (WM) analysis results show that the unwanted switching of the unselected cell during the write operation is unlikely in the 1S1R CBA even with a large N value, despite a voltage drop along the interconnection wire. The analysis of simultaneous multiply‐and‐accumulate operations is conducted using the analytical method to examine the influence of voltage drop according to the wire and memory cells in HNN applications. Reducing the wire resistance and on‐state conductance increases the available N value when the selector operates near the threshold conditions. The proposed analytical model can estimate the maximum accuracy degradation of the HNN through the involvement of the unintentional voltage drop.

Keywords

• crossbar arrays
• IR drop
• neural networks
• one selector–one resistor
• simulation models