Optimal design of 10‐bit single‐slope ADC for CMOS image sensor based on swarm intelligent optimization algorithm

Abstract

Abstract As one of the most critical blocks of the CMOS image sensor (CIS), the accuracy and power consumption of the analogue‐to‐digital converter (ADC) play an important role in its performance. However, due to the mutually restrictive relationship between power consumption and accuracy in the single‐slope ADC (SS ADC), it is difficult to improve these performance indexes meantime without an efficient optimal design method. Here, an optimal design methodology based on an improved artificial fish swarm optimization algorithm (IAFSOA) is proposed for a 10‐bit SS ADC in CIS. First, a voltage storage structure and offset calibration circuit are developed for promoting the performance of the comparator. Then, IAFSOA is developed for the circuit parameters optimization with faster convergence rate and higher computational accuracy. The proposed multi‐objectives optimization algorithm can obtain the optimal parameters of the kernel circuit components and lead to an enhancement of both power consumption and accuracy. The optimized SS ADC is designed based on 0.18 µm process to verify the effectiveness of the proposed method. Compared to the earlier reported work, the IAFSOA‐based optimal design method can promote the performance of the SS ADC by an improvement of effective number of bits and a reduction of power consumption.

Keywords

• analogue-digital conversion
• calibration
• low-power electronics
• CMOS image sensors
• particle swarm optimisation
• optimisation