Hardware Architecture for Reducing Worst-Case Latency in Fast SCF Polar Decoders

Abstract

The Successive Cancellation Flip (SCF)-based decoding for polar codes requires significant latency at low SNRs. This paper proposes a low-latency SCF-based decoding and decoder architecture based on decoding history. In particular, a history memory structure for the Fast-SCF (FSCF) decoder has been proposed. The proposed history memory can store the intermediate decoding result of the first decoding and reduce the latency by shortening the additional decoding distance of SCF-based decoding. Furthermore, codeword segmentation is used to compensate for the area increase due to the history memory. The proposed decoder was synthesized using the Samsung 28 nm standard cell library and compared with state-of-the-art polar decoders. The proposed History-based FSCF (HFSCF) decoder improved the worst-case throughput, and the result was approximately doubled compared to FSCF decoders that share the same decoder architecture. In addition, the normalized worst-case area efficiency was 78% higher than the FSCF decoder with the same flipping trial and 22% higher than the latest Belief Propagation Flip (BPF) decoder.

Keywords

• Polar codes
• 5G
• decoding history
• worst-case latency
• successive cancellation flip (SCF)
• hardware architecture