Time-Delay Correction Control Strategy for HVDC Frequency Regulation Services

Abstract

With the advancements in voltage source converter (VSC) technology, VSC based high voltage direct current (VSC-HVDC) systems provide system operators with a prospective approach to enhance system operating stability and resilience. In addition to long-distance transmission, the VSC-HVDC system can also provide multiple ancillary services, such as frequency regulation, due to its power controllability. However, if a time delay exists in the control signal, the VSC-HVDC system may bring destabilizing influences to the system, which will decrease the system resilience under the disturbance. In order to reduce control deviation caused by time delay, in this paper, a small signal model is first conducted to analyze the impact of time delay on system stability. Then a time-delay correction control strategy for HVDC frequency regulation control is developed to reduce the influence of the time delay. The control performance of the proposed time-delay correction control is verified both in the established small signal model and the runtime simulation in a modified IEEE 39 bus system. The results indicate that the proposed time-delay correction control strategy shows significant improvement in system stability.

Keywords

• Frequency regulation control
• HVDC
• small signal analysis
• time delay
• time-delay correction control strategy