Double-Sided Fabrication of Low-Leakage-Current Through-Silicon Vias (TSVs) with High-Step-Coverage Liner/Barrier Layers

Abstract

In this paper, a novel through-silicon via (TSV) fabrication strategy based on through-hole structures is proposed for low-cost and low-complexity manufacturing. Compared to conventional TSV fabrication processes, this method significantly simplifies the process flow by employing double-sided liner deposition, double-sided barrier layer/seed layer formation, and double-sided Cu electroplating. This method enhances the TSV stability by eliminating Cu contamination issues during chemical–mechanical polishing (CMP), which are a common challenge in traditional blind via fabrication processes. Additionally, the liner and barrier layer/seed layer achieve a high step coverage exceeding 80%, ensuring excellent conformality and structural integrity. For electroplating, a multi-stage bi-directional electroplating technique is introduced to enable void-free Cu filling in TSVs. The fabricated TSVs exhibit an ultra-low leakage current of 135 fA at 20 V, demonstrating their potential for advancing 3D integration technologies in heterogeneous integration.

Keywords

• through-silicon via
• parylene liner
• double-sided process
• electroless plating
• electroplating