EMPLOYING COMPLEXITY ESTIMATES OF BINARY DECISION DIAGRAMS IN THE SYNTHESIS OF LOGICAL CIRCUITS

Abstract

A formula is suggested to evaluate the area of a logical circuit that is built in a given library of logical elements according to the BDD (Binary Decision Diagram) representation of a system of Boolean functions. The experimental results of synthesis of combinational logical circuits from the minimized BDD representations in the design library of custom CMOS VLSI circuits are described.