Vertical GaN Power MOSFET with Integrated Fin-Shaped Diode for Reverse Conduction

Tao Sun; Xiaorong Luo; Jie Wei; Kemeng Yang; Siyu Deng; Zhijia Zhao; Yanjiang Jia; Bo Zhang

doi:10.1186/s11671-022-03717-0

Nanoscale Research Letters (Aug 2022)

Vertical GaN Power MOSFET with Integrated Fin-Shaped Diode for Reverse Conduction

Tao Sun,
Xiaorong Luo,
Jie Wei,
Kemeng Yang,
Siyu Deng,
Zhijia Zhao,
Yanjiang Jia,
Bo Zhang

Affiliations

Tao Sun: State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China
Xiaorong Luo: State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China
Jie Wei: State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China
Kemeng Yang: State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China
Siyu Deng: State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China
Zhijia Zhao: State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China
Yanjiang Jia: State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China
Bo Zhang: State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China

DOI: https://doi.org/10.1186/s11671-022-03717-0
Journal volume & issue: Vol. 17, no. 1
pp. 1 – 6

Abstract

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Abstract A vertical GaN power MOSFET featuring an integrated fin-shaped non-junction diode (FDMOS) is proposed to improve reverse conduction and switching characteristics. Its static and dynamic characteristics are studied and analyzed by Sentaurus TCAD simulation. Compared with the conventional MOSFET (Con. MOS) with a body diode as a freewheeling diode (FWD), the FDMOS uses the integrated fin-shaped diode to reverse conduction, and thus, a low reverse turn-on voltage V ON of 0.66 V is achieved, with a decreasing of 77.9%. Moreover, the Q rr of the FDMOS is reduced to 1.36 μC from 1.64 μC of the Con. MOS, without the minority carrier injection. The gate charge (Q GD) of the FDMOS is significantly reduced because the fin structure reduces the gate area and transforms some part of C GD to C GS, and thus, a low switching loss is realized. The Q GD, the turn-on loss (E on) and the turn-off loss (E off) of the FDMOS are decreased by 56.8%, 33.8% and 53.8%, respectively, compared with those of the Con. MOS. In addition, the FDMOS is beneficial to reduce the parasitic inductance and the total chip area compared with the conventional method of using an externally connected Schottky diode as an FWD.

Published in Nanoscale Research Letters

ISSN: 1931-7573 (Print); 1556-276X (Online)
Publisher: SpringerOpen
Country of publisher: United Kingdom
LCC subjects: Technology: Electrical engineering. Electronics. Nuclear engineering: Materials of engineering and construction. Mechanics of materials
Website: https://www.springer.com/journal/11671

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