Approaches to the SoC IP-Blocks' design with errors' mitigation

Abstract

Developing of failsafe systems is the problem solving in different sectors. Hardware design is not an exception. This sector imposes additional requirements constructing failover controllers, such as chip area and energy consumption. This article provides types and causes of errors to define their effect on SoC and offers the general idea of errors resilient SoC that consists of error detecting, error fixing and error mitigating mechanism. Also in the paper reconfiguration is considered as the error mitigation mechanism and methods used in practice to implement reconfiguration are presented. Before producing controller or other IP-block with error mitigation, first of all it is necessary to assess possible variants of failure and ways to improve its failsafe. Therefore methods of failure assessments are presented. As the result - Markov chain is chosen as the assessment tool and example of constructing of Markov chain for not reconfigurable and reconfigurable controller of transport layer protocol is presented. Comparative analyses of the results are carried out.

Keywords

• error mitigation
• Reconfigurable system-on-chip
• Reconfigurable network-on-chip (NoC)
• Markov Chain
• reliability