Automatic simulation method for functional equivalence check

Abstract

In the mixed-signal chip, behavioral model is widely used to describe the behavior of the analog/mixed-signal blocks in Verilog/Systemverilog/VHDL so as to facilitate the fullchip netlisting for the fullchip Verilog simulation. In order to ensure correct，effective and comprehensine function verification of full chip，functional comparison and verification between behavioral module and transistor-level design of circuit module is very important. Currently, BVS is verified only through the logic state vector check with existing official EDA tools without real value checking. To better describe the analog/mixed-signal blocks behavior, Wreal modeling and SV-UDT are used, thus BVS check with real type vector check capability is required. This paper describes an automatic simulation method for equivalence check of both real value auto compare and logic state auto compare based on XPS vector check feature, the real type vector check is new idea provided to EDA vendor and has already been implemented in XPS successfully.

Keywords

• functional equivalence check
• bvs
• wreal modeling
• real type vector check
• xps