FiCA: A Fixed-Point Custom Architecture FastICA for Real-Time and Latency-Sensitive Applications

Abstract

Independent Component Analysis (ICA) is a common method exploited in different biomedical signal processing applications, especially in noise removal of electroencephalography (EEG) signals. Among different existing ICA algorithms, FastICA is a popular method with less complexity, which makes it more suitable for practical implementation. However, and due to its inherent computationally intensive nature, development of a custom FastICA hardware is the best way to utilize it in high-performance real-time applications. On the other hand, development of a custom hardware in a fixed-point manner is also a complex and challenging task due to the algorithm’s iterative nature. Moreover, the algorithm intrinsically suffers from some convergence problems which prevents to be practically exploited in latency-sensitive applications. In this paper, a fixed-point fully customized, scalable, and high-performance FastICA processor architecture has been presented. The proposed architecture is developed in an algorithm-aware manner to mitigate the inherent FastICA algorithmic failures. The synthesis results in a 90 nm technology show that the design proposes a computational time of 0.32 ms to perform an 8-channel ICA with a frequency of 555 MHz. The performance-related measurements prove that its normalized throughput is 10 times more, compared to the closest rival.

Keywords

• Artefact detection
• brain-computer interface
• EEG
• FastICA
• fixed-point arithmetic
• independent component analysis