Consumer Document Analytical Accelerator Hardware

Abstract

Document scanning devices are used for visual character recognition, followed by text analytics in the software. Often such character extraction is insecure, and any third party can manipulate the information. On the other hand, near-edge processing devices are restrained by limited resources and connectivity issues. The primary factors that lead to exploring independent hardware devices with natural language processing (NLP) capabilities are latency during cloud processing and computing costs. This paper introduces a hardware accelerator for information retrieval using memristive TF-IDF implementation. In this system, each sentence is represented using a memristive crossbar layer, with each column containing a single word. The number of matching scores for the TF and IDF values was implemented using operational amplifier-based comparator accumulator circuits. The circuit is designed with a 180nm CMOS process, Knowm Multi-Stable Switch memristor model, and WOx device parameters. We compared its performance with that of a standard benchmark dataset. Variability and device-to-device related issues were also taken into consideration in the analysis. This paper concludes with implementing TF-IDF score calculation for applications such as information retrieval and text summarization.

Keywords

• Natural language processing
• TF-IDF
• hardware accelerator
• memristive systems
• memristor
• analog computation