FPGA-Based Improved Background Subtraction for Ultra-Low Latency

Abstract

In recent years, advancements in telecommunication technology have led to the proliferation of high-speed, large-capacity, low-latency communication. The COVID-19 pandemic has also accelerated the adoption of remote work globally, making real-time remote communication applications like web conferencing crucial for business, education, and other sectors. Despite the various demands for streaming applications, existing services often fail to meet the requirements of scenarios demanding ultra-low latency, such as surgical operations, remote control of automobiles, and real-time collaborative performances. To address this, we explored using FPGAs to achieve ultra-low latency processing in image processing tasks, explicitly focusing on background removal. Our study demonstrated the feasibility of using commercially available FPGA devices to reduce latency in background subtraction significantly compared to conventional methods. The results indicate that FPGA-based processing can provide the ultra-low latency needed for critical applications, enhancing the performance and user experience in remote operations and real-time streaming.

Keywords

• FPGA
• hardware direct implementation
• low-latency
• stream processing
• background subtraction
• background removal