Ferroelectric Field‐Effect‐Transistor Integrated with Ferroelectrics Heterostructure

Abstract

Abstract To address the demands of emerging data‐centric computing applications, ferroelectric field‐effect transistors (Fe‐FETs) are considered the forefront of semiconductor electronics owing to their energy and area efficiency and merged logic–memory functionalities. Herein, the fabrication and application of an Fe‐FET, which is integrated with a van der Waals ferroelectrics heterostructure (CuInP2S6/α‐In2Se3), is reported. Leveraging enhanced polarization originating from the dipole coupling of CIPS and α‐In2Se3, the fabricated Fe‐FET exhibits a large memory window of 14.5 V at VGS = ±10 V, reaching a memory window to sweep range of ≈72%. Piezoelectric force microscopy measurements confirm the enhanced polarization‐induced wider hysteresis loop of the double‐stacked ferroelectrics compared to single ferroelectric layers. The Landau–Khalatnikov theory is extended to analyze the ferroelectric characteristics of a ferroelectric heterostructure, providing detailed explanations of the hysteresis behaviors and enhanced memory window formation. The fabricated Fe‐FET shows nonvolatile memory characteristics, with a high on/off current ratio of over 106, long retention time (>104 s), and stable cyclic endurance (>104 cycles). Furthermore, the applicability of the ferroelectrics heterostructure is investigated for artificial synapses and for hardware neural networks through training and inference simulation. These results provide a promising pathway for exploring low‐dimensional ferroelectronics.

Keywords

• ferroelectric semiconductors
• ferroelectronics
• van der Waals ferroelectric heterostructures