VHDL Modelling of Low-Cost Memory Fault Detection Tester

Abstract

Memory modules are widely used in varies kind of electronics system design. Thecapacity of the memory moduleshas increased rapidly since the past few years in order to satisfy the high demand from the end-users.The memory modules’ manufacturersdemand more units of automatic test equipment (ATE)to increase the production rate. However, the existing ATE used inthe industry to carry out thememory testing istoo costly(at least a million dollarsper ATE tester). The low-cost memory testers are urgently needed to increase the production rate of the memory module.This has inspiredus to design a low-costmemory tester.A low-cost memory fault detection tester withall the majorfault detection algorithms that used in industry ismodelled using Very High Speed Integrated Circuit Hardware Description Language (VHDL) in this paper to support the need of the low-cost ATE memory tester. The fault detection algorithms modelled are MATS+ (Modified Algorithm Test Sequence), MATS++, March C, March C-, March X,March Y,zero-one and checkerboard scan tests. PERL programisused to analyse the simulation results and a log file will be generated at the end of the memory test. Extensive simulation and experimental test results show that the memory tester modelled covers all thememory test algorithmsused in the industry.The low-cost memory fault detection tester designed providesthe 100% fault detection coverage for all memory defects.

Keywords

• vhdl
• memory tester
• march test