Highly Versatile FPGA-Implemented Cyber Coherent Ising Machine

Abstract

To solve large-scale real-world problems, attempts have been made to realize high-speed simulations of quantum Ising machines using field-programmable gate arrays (FPGAs) and to virtually realize networks with a large number of fully coupled spins, which are difficult to achieve in physical systems. We developed an FPGA-implemented cyber coherent Ising machine (cyber CIM) that is much more versatile than previous implementations using FPGAs. Our architecture is versatile because it can be applied to the open-loop CIM, which was proposed when CIM research began, to the closed-loop CIM, which has been used recently, and to the Jacobi successive over-relaxation method. By modifying the sequence control code for the calculation control module, other algorithms such as Simulated Bifurcation (SB) can also be implemented. Earlier studies on large-scale FPGA implementations of SB and CIM used binary or ternary discrete values for connections, whereas cyber CIM used single-precision floating-point format (FP32) values. In addition, cyber CIM uses Zeeman terms that are represented in FP32, which are not present in other large-scale FPGA systems. Our implementation with continuous interaction achieves $N=4096$ on a single FPGA, which is comparable to the single-FPGA implementation of SB with binary interactions with $N=4096$ . Cyber CIM enables applications such as code division multiple access multi-user detector and L0-norm regularization-based compressed sensing which were not possible with earlier FPGA systems, while providing superior calculation speeds, more than ten times faster than the graphic processor unit (GPU) implementation. Increasing parallelism, such as through clustering, can further enhance the calculation speed.

Keywords

• Coherent Ising machine
• FPGA
• versatile architecture
• combinatorial optimization
• compressed sensing