Field programmable gate array (FPGA) implementation of novel complex PN-code-generator- based data scrambler and descrambler

Abstract

A novel technique for the generation of complex and lengthy code sequences using low- length linear feedback shift registers (LFSRs) for data scrambling and descrambling is proposed. The scheme has been implemented using VHSIC hardware description language (VHDL) approach which allows the reconfigurability of the proposed system such that the length of the generated sequences can be changed as per the security requirements. In the present design consideration the power consumption and chip area requirements are small and the operating speed is high compared to conventional discrete I.C. design, which is a pre-requisite for any system designer. The design has been synthesised on device EP2S15F484C3 of Straitx II FPGA family, using Quarts Altera version 8.1. The simulation results have been found satisfactory and are in conformity with the theoretical observations.

Keywords

• complex code generator
• VHDL
• FPGA
• scrambler
• descrambler