Hybrid Timing Error Detector for Baud Rate Multilevel Clock and Data Recovery

Abstract

This paper proposes a hybrid phase detector for use in multilevel timing recovery systems. The proposed approach suppresses errant zero-crossings associated with multilevel baud rate phase detectors and ensures maximum signal swing in lock, with minimal hardware and power overhead. Analysis and simulation results in a 28nm CMOS process are used to explore the functionality of proposed phase detector and demonstrate its effectiveness in achieving superior performance to the conventional approach.Clock and data recovery (CDR) loop simulations show that the proposed phase detector enables $1.36\times $ increase in vertical eye margin while maintaining similar steady-state RMS jitter and compared to the conventional approach. The simulations also show effective suppression of unwanted phase detector zero-crossing, while achieving comparable acquisition bandwidth to the conventional approach.

Keywords

• Hybrid phase detection
• slope-sensitive latch
• time-domain interpolation
• multilevel signaling
• StrongArm latch
• clock and data recovery