Novel Observations and Physical Insights on PSIJ Behavior in CMOS Chain-of-Inverters

Abstract

This paper presents novel observations and physical insights on jitter in a chain of CMOS inverters. It is demonstrated that at the final output of the inverter chain, power supply induced jitter does not necessarily increase with the number of inverter stages. The presented investigation is validated by comparing the results using a semianalytical method with SPICE based simulations. The proposed observations are also validated using measurement results obtained by two measurement setups.

Keywords

• CMOS inverter
• chain of inverters
• delay-line
• jitter
• power supply induced jitter