Yuanzineng kexue jishu (Apr 2022)
Research and Evaluation on SEM-based FPGA Anti-SEU Solution
Abstract
With the development of aerospace avionics, there is an increasing demand for high performance chips to handle data processing and transmission requirements. In recent years, the SRAM�based FPGAs have been widely used in on�board data processing systems for their abundant performance and high flexibility. However, compared to the anti�fuse FPGAs, the SRAM�based FPGAs are more vulnerable to the single error events (SEE), especially to the single error upsets (SEU) in space. This disadvantage restricts the SRAM�based FPGAs to be applied in on�board systems with high reliability requirements. There are quite a lot of studies in this area, trying to improve the anti�SEU performance for the SRAM�based FPGAs. Most of the researches focus on the anti�SEU design for the configuration RAM inside the FPGAs, for soft errors occurred in the configuration RAM can lead to more serious functional problems than any other parts in the FPGAs. With the technical advances of on�chip error detection and correction methods, Xilinx has introduced a new type of soft error mitigation (SEM) method on its SRAM�based FPGA. The SEM uses internal scrubber architecture, which relies on the on�chip error correction code (ECC) and the cyclic redundancy check (CRC) calculation circuits to detect and repair soft errors occurred in the configuration RAM. Compared to the traditional external scrubber architecture, internal scrubber is much more efficient due to its faster on�chip datapath and calculation circuits, which leads to better soft error rate performance in orbit. However, the SEM core is still built up by the SEU�vulnerable logic and memory resources in the FPGA, which may lead to certain risk of soft error problems. As a result, it is necessary to develop a systematical method to deal with the possible failure of the SEM core with as low cost as possible. In this paper, an analysis on the necessity and possible problems of applying the SEM technique was provided and a solution to handle the SEM core’s failure by introducing an external monitor was proposed. The monitor was implemented in an anti�fuse FPGA to ensure reliability and would only reprogram the FPGA when SEM failure was detected, leaving most ordinary soft errors to be handled by SEM core efficiently. Thus, both goals of high efficiency and high reliability were achieved. The solution is applied on a XC7K410T FPGA and verified by the SEE tests with heavy ions.
