Low-Stray Inductance Optimized Design for Power Circuit of SiC-MOSFET-Based Inverter

Abstract

High frequency converters based on silicon carbide (SiC) semiconductors are becoming popular, but due to the integration parameters, they are very likely to generate high voltage overshoot and large oscillation, which increase the voltage stress and cause EMC problems. To suppress the voltage overshoot and oscillation, the mechanism is firstly analyzed. Stray inductance is a culprit in causing these problems. To minimize the inductance of power circuit, this paper proposes optimization method including better design of bus-bar structure and parallel connection of snubber capacitors by means of model analysis and formula derivation. To evaluate the method, an inverter model and a prototype were built, several optimization schemes were compared by co-simulation and experimental tests. Experimental results show that the stray inductance of the new bus-bar is 6.4% of the traditional bus-bar. The loop-inductance can be reduced by 46.4% by connecting the capacitors in parallel, and the switching losses can be reduced by 30.8%. This analysis provides guidelines for a full SiC inverter design.

Keywords

• SiC-MOSFET
• low stray inductance
• design method
• double-pulse test