A non-linear analytic stress model for the analysis on the stress interaction between TSVs

Abstract

Thermo-elastic strain is induced by through silicon vias (TSV) due to the difference of thermal expansion coefficients between the copper (∼18 ppm/◦C) and silicon (∼2.8 ppm/◦C) when the structure is exposed to a thermal budget in the three dimensional integrated circuit (3DIC) process. These thermal expansion stresses are high enough to induce the delamination on the interfaces between the copper, silicon, and isolated dielectric. A compact analytic model for the strain field induced by different layouts of thermal copper filled TSVs with the linear superposition principle is found to result in large errors due to the strong stress interaction between TSVs. In this work, a nonlinear stress analytic model with different TSV layouts is demonstrated by the finite element method and Mohr’s circle analysis. The stress characteristics are also measured by the atomic force microscope-raman technique at a nanometer level resolution. This nonlinear stress model for the strong interactions between TSVs results in an electron mobility change ~2-6% smaller than that resulting from a model that only considers the linear stress superposition principle.

Keywords

• Nonlinear analytic modeling
• strain field
• through silicon via (TSV)