An improved digital phase locked loop against adverse grid conditions

Abstract

The phase-locked loop (PLL) is an essential synchronization technique to ensure stable operation and control of grid-connected converters. Nevertheless, under actual conditions, the grid voltage is often influenced by harmonics and frequency variation, resulting in unsatisfactory steady-state precision and dynamic performance of the PLL. Therefore, in this paper, an improved digital PLL (ID-PLL) including harmonics elimination module and angular frequency reference calculation module is proposed. The proposed ID-PLL can maintain steady-state precision and dynamic performance in the condition of voltage unbalance, voltage harmonics and voltage frequency variation. The influence of adverse grid voltage on PLL performance is analyzed in detail. The parameters design and discretization approach is presented accordingly. The effectiveness of the proposed approach is confirmed by compared experiments with DSOGI-PLL.

Keywords

• Adverse grid conditions
• SRF-PLL
• ID-PLL
• Harmonics elimination
• Frequency adaption