Energy Science & Engineering (Aug 2021)

Advanced textured monocrystalline silicon substrates with high optical scattering yields and low electrical recombination losses for supporting crack‐free nano‐ to poly‐crystalline film growth

  • Thierry deVrijer,
  • Arno H. M. Smets

DOI
https://doi.org/10.1002/ese3.873
Journal volume & issue
Vol. 9, no. 8
pp. 1080 – 1089

Abstract

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Abstract Crystalline silicon tandem devices with perovskites, CIGS, and nanocrystalline silicon, as well as the TOPCon design, are incompatible with the conventional pyramidal surface texture of silicon. This is a result of crack formation in nano to polycrystalline growth on large sharp surface features. In this work, three texturing approaches are investigated, using alkaline and/or acidic wet chemical etches, that can lead to the crack‐free growth of nano to polycrystalline materials on textured surfaces. In this work, we show that without acidic smoothening, the fraction of pyramidal surface coverage has to remain relatively small to prevent crack formation during crystalline growth on these surfaces. Applying an acidic etch as a function of time continuously smoothens surface features. This shifts the reflection to wider scattering angles and results in higher total reflected intensity with respect to the conventional texture, making it an interesting option for a wide variety of tandem pv applications. Finally, we demonstrate crater‐like features on a monocrystalline silicon surface using an etching process including a sacrificial layer. These craters increase light scattering into wider angles, but to a lesser extent than the former approach. In terms of passivation, we demonstrate the positive effect of a post deposition hydrogen treatment. Initial dilution of the silane plasma improves passivation on a surface, but is detrimental to passivation on a surface, likely because the hydrogen dilution results in epitaxial growth at the c‐Si/a‐Si:H hetero‐interface. A minority carrier lifetime of over 3 ms has been achieved for all texturing approaches, after deposition of a 15 nm a‐Si:H layer on both sides of the wafer, for different a‐Si:H deposition and annealing schemes.

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