Low Power and High Speed DFT Architecture

Abstract

Discrete Fourier Transform (DFT) plays essential role in many signal processing applications. In this paper, novel hardware architecture is presented for DFT. It is based on various transform sizes (N) in aim to provide low power and high speed for modern multimedia applications. The proposed architecture uses two Multipliers and adders to perform the computation of DFT for different sizes of input data. Full analysis of architecture is discussed thoroughly for various transform sizes (N). This analysis consists of power consumption, hardware cost and speed parameters discussion. In addition, the implementation of this architecture in Field Programmable Gate Arrays (FPGA) is explained. Less than 1.62 mW dynamic power consumption for N=128 at 100 MHz operating frequency is achieved by proposed architecture. Finally, the comparison with state of art architectures results reveals that the proposed architecture outperforms other architectures in terms of speed and hardware cost.

Keywords

• Verilog-HDL
• DFT
• Synchronous Dataflow Graph (SDFG)