Comprehensive Modeling of the Depletion-mode MOS Capacitor for Circuit Simulation

Abstract

A comprehensive model is developed for a MOS capacitor implemented using an n-channel depletion-mode MOSFET fabricated in a submicron CMOS technology, which accounts for the voltage dependence of the MOS capacitance over the entire range of operating voltages. Notably, the model, whose active component is derived based on the industry-standard BSIM3 MOSFET model, fits the measured capacitance-voltage data with a goodness of fit characterized by coefficient of correlation of 0.99. By considering the gate capacitance and the associated series resistance as a distributed RC network, a realistic compact subcircuit representation is obtained for the MOS capacitor, which allows modeling of the limitations imposed by the series resistance on high-frequency performance as well as the quality factor. The model is also validated based on SPICE simulations with the channel resistance associated with the inversion layer modeled as a voltage-controlled resistor in order to account for the nonlinearity of the parasitic series resistance associated with the MOS capacitor.

Keywords

• mos capacitor
• depletion-mode mosfet
• bsim3 model
• charge thickness model