Challenges to adopting adiabatic circuits for systems‐on‐a‐chip

Abstract

Abstract Adiabatic complementary metal–oxide–semiconductor (CMOS) circuits have been proposed as a low‐power option for CMOS systems‐on‐a‐chip (SoCs) but have not gained popularity due to practical difficulties in scaling to millions of gates. The architecture of a pipeline of stages with slow‐transitioning clock phases demands the generation and distribution of clock phases precisely and efficiently. This power must be more than offset by the power saved by using adiabatic circuits. The problems in adiabatic logic circuits are described, and solutions are proposed to address them. Three published topologies are considered, namely positive‐feedback adiabatic logic (PFAL), two‐level adiabatic logic (2‐LAL) and clocked adiabatic logic in 40 nm CMOS technology at 100 MHz. New circuit ideas for complete level restore in PFAL and avoidance of floating nodes in 2‐LAL are presented. The problem with 2‐LAL multi‐input gates is published and solved for the first time here using a modified PFAL. The conclusion is that a 3X power savings in PFAL is about the best that can be achieved in an SoC context—a low return given the required investments in area and complexity. This should motivate the future discovery of more efficient solutions.

Keywords

• clocks
• CMOS logic circuits
• logic design
• low‐power electronics
• system‐on‐chip